Winbond, SDRAM, 2 Gb, Overflade 16 bit, 95 °C, -40 °C, 84 Ben, WBGA
- RS-varenummer:
- 188-2584
- Producentens varenummer:
- W972GG6KB25I
- Brand:
- Winbond
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- RS-varenummer:
- 188-2584
- Producentens varenummer:
- W972GG6KB25I
- Brand:
- Winbond
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Vælg alle | Attribut | Værdi |
|---|---|---|
| Brand | Winbond | |
| Bilindustristandarder | Nej | |
| Produkttype | SDRAM | |
| Hukommelsesstørrelse | 2 Gb | |
| Monteringstype | Overflade | |
| Databusbredde | 16 bit | |
| Driftstemperatur maks. | 95 °C | |
| Min. driftstemperatur | -40 °C | |
| Benantal | 84 | |
| Emballagetype | WBGA | |
| Adressebusbredde | 17 bit | |
| Højde | 600 μm | |
| Længde | 12.6 mm | |
| Klokfrekvens maks. | 533 MHz | |
| Random access-tid maks. | 0.4 ns | |
| Forsyningsspænding maks. | 1.9 V | |
| Forsyningsspænding min. | 1.7 V | |
| Antal Bits per ord | 8 | |
| Antal ord | 256M | |
| Organisation | 256 M x 8 bit | |
| Serie | W972GG6KB | |
| Standarder/godkendelser | RoHS | |
| Forsyningsstrøm | 280 mA | |
| Bredde | 8.1 mm | |
| Vælg alle | ||
|---|---|---|
Brand Winbond | ||
Bilindustristandarder Nej | ||
Produkttype SDRAM | ||
Hukommelsesstørrelse 2 Gb | ||
Monteringstype Overflade | ||
Databusbredde 16 bit | ||
Driftstemperatur maks. 95 °C | ||
Min. driftstemperatur -40 °C | ||
Benantal 84 | ||
Emballagetype WBGA | ||
Adressebusbredde 17 bit | ||
Højde 600 μm | ||
Længde 12.6 mm | ||
Klokfrekvens maks. 533 MHz | ||
Random access-tid maks. 0.4 ns | ||
Forsyningsspænding maks. 1.9 V | ||
Forsyningsspænding min. 1.7 V | ||
Antal Bits per ord 8 | ||
Antal ord 256M | ||
Organisation 256 M x 8 bit | ||
Serie W972GG6KB | ||
Standarder/godkendelser RoHS | ||
Forsyningsstrøm 280 mA | ||
Bredde 8.1 mm | ||
The W972GG6KB is a 2G bits DDR2 SDRAM, and speed involving -18, -25/25I, and -3/-3I.
Double Data Rate architecture: two data transfers per clock cycle
CAS Latency: 3, 4, 5, 6 and 7
Burst Length: 4 and 8
Bi-directional, differential data strobes (DQS and /DQS ) are transmitted / received with data
Edge-aligned with Read data and center-aligned with Write data
DLL aligns DQ and DQS transitions with clock
Differential clock inputs (CLK and /CLK)
Data masks (DM) for write data
Commands entered on each positive CLK edge, data and data mask are referenced to both edges of /DQS
Posted /CAS programmable additive latency supported to make command and data bus efficiency
Read Latency = Additive Latency plus CAS Latency (RL = AL + CL)
Off-Chip-Driver impedance adjustment (OCD) and On-Die-Termination (ODT) for better signal quality
Auto-precharge operation for read and write bursts
Auto Refresh and Self Refresh modes
Precharged Power Down and Active Power Down
Write Data Mask
Write Latency = Read Latency - 1 (WL = RL - 1)
Interface: SSTL_18