CY14V101QS-SF108XI, NVRAM, 1Mbit, Overflademontering, 16 Ben, SOIC

The Cypress CY14V101QS combines a 1-Mbit nvSRAM with a QPI interface. The QPI allows writing and reading the memory in either a single (one I/O channel for one bit per clock cycle), dual (two I/O channels for two bits per clock cycle), or quad (four I/O channels for four bits per clock cycle) through the use of selected opcodes. The memory is organized as 128Kbytes each consisting of SRAM and nonvolatile SONOS Quantum Trap cells. The SRAM provides infinite read and write cycles, while the nonvolatile cells provide highly reliable storage of data. Data transfers from SRAM to the nonvolatile cells (STORE operation) take place automatically at power-down. On power-up, data is restored to the SRAM from the nonvolatile cells (RECALL operation). You can also initiate the STORE and RECALL operations through SPI instructions.